1. Field of the Invention
The present invention relates to a memory system provided with a memory operating in synchronization with a clock signal.
2. Description of the Background Art
FIG. 8 shows the structure of a conventional memory system. As shown in FIG. 8, a clock generator 50 included in a memory controller 5 generates a clock signal Ck0. This clock signal Ck0 is transferred through a clock signal line 7 to be input to a memory 1 as clock signal Ck1, to a memory 2 as clock signal Ck2, to a memory 3 as clock signal Ck3, and to a memory 4 as clock signal Ck4. Memories 1 to 4 operate in synchronization with corresponding clock signals Ck1 to Ck4.
A data bus 9 transfers write data output from memory controller 5 to memories 1 to 4, and read data output from memories 1 to 4 to memory controller 5. In other words, data bus 9 transfers data bidirectionally.
A control signal for memories 1 to 4 is output from memory controller 5 and transferred through a control signal bus 11 to memories 1 to 4.
In such a memory system carrying out synchronizing operation as described above, however, a skew between a clock signal and data is produced as a frequency of the clock signal is increased, causing malfunction.
In addition, a larger skew between a clock signal and data is produced in a larger system in which the distance between a memory controller and a memory is larger.
FIG. 9A-9E are timing charts showing the timing of clock signals Ck1 to Ck4 respectively input to memories 1 to 4 shown in FIG. 8.
Clock signal Ck0 output from memory controller 5 delays in transmission through clock signal line 7. Therefore, clock signal Ck0 with larger delay is input to a memory located at a greater distance away from memory controller 5 which is a clock signal source. Accordingly, clock signals Ck1 to Ck4 have longer delay time with respect to clock signal Ck0 in this order, as shown in FIGS. 9A-9E. As a result, even if memories 1 and 4 for example trigger operation in response to the same timing edge of clock signal Ck0 output from memory controller 5, these two memories 1 and 4 start operating at a different time.
FIGS. 10A-10F are timing charts for use in illustration of data transfer in memories 1 and 4. Note that it is herein assumed that memories 1 and 4 have the same performance.
As shown in FIG. 10B and FIG. 10C, data D1-1 and D1-2 are successively output from memory 1 onto data bus 9 in accordance with clock edges (rising edges, in this case) t2 and t3 of clock signal Ck1 after the passage of time ta from rising edges t1 and t2 of clock signal Ck1 respectively.
In this case, as shown in FIG. 10D and FIG. 10E, data D4-1 and D4-2 are successively output from memory 4 onto data bus 9 in accordance with clock edges (rising edges, in this case) t6 and t7 of clock signal Ck4 after the passage of time ta from rising edges t5 and t6 of clock signal Ck4, respectively.
Clock signals Ck1 and Ck4, however, result from the same clock signal Ck0, generated at clock generator 50, being input to memories 1 and 4, respectively. Time tc1 indicates signal delay time between memory controller 5 and memory 1, and time ta indicates data access time of a memory from a clock edge. In addition, time tc4 indicates signal delay time between memory controller 5 and memory 4.
As shown in FIG. 10B and FIG. 10C, data D1-1 is output from memory 1 in response to clock edge (rising edge, in this case) t1 of clock signal Ck1. And as shown in FIG. 10A and FIG. 10F, the data reaches the point C of FIG. 8 after delay time (tc1+ta+tc1) and is input to memory controller 5. Since memory 1 is close in position to memory controller 5, memory controller 5 can receive data D1-1 in accordance with clock edge (rising edge) t2 of clock signal Ck0 as trigger. However, memory 4 is located far away from memory controller 5 and therefore time tc4 is longer than time tc1. Accordingly, memory controller 5 cannot receive data D4-1 output from memory 4 in response to clock edge t5 of clock signal Ck4 as shown in FIG. 10D and FIG. 10E in accordance with clock edge t6 of clock signal Ck0 as trigger.
Thus, it is difficult for memory controller 5 in a high-speed memory system to receive data output from each memory at fixed timing. More specifically, in a memory system satisfying time tclk&lt;time (tcm+ta+tcm) wherein tcm indicates signal delay time between a memory and memory controller 5 which is a clock signal source, ta indicates time for data access in the memory, and tclk indicates the cycle of the clock signal, the timing skew of data output from each memory into memory controller 5 exceeds one cycle of the clock signal. Accordingly, memory controller 5 cannot always receive data in accordance with the clock edge subsequent to that for outputting data from the memory.
Thus, in the conventional memory system, the need for a higher data transfer rate and an increased frequency of the clock signal give rise to the problem of the timing skew between data output from each memory and the clock signal.
Then, in order to eliminate the skew between the clock signal and data, it is possible to output a clock signal from a memory in synchronization with output data at the time of data output of the memory. In this case, however, the memory must be redesigned to include a clock signal generating circuit and an output buffer, leading to increase in chip area.
Furthermore, it is also possible to reduce the timing skew between clock signal and data using two kinds of clock signals, that is, clock signals for data input and for data output. In this case, however, the memory must be redesigned to independently include an input clock pin and an output clock pin in a memory device, leading to increase in chip area.
In addition, as shown in FIG. 8, data bus 9 in the conventional memory system is a bus for bi-directional data transfer, and an increased operating frequency might cause conflict of data moving in different directions.
FIG. 11A-11D are timing charts showing data conflict in data bus 9.
As shown in FIG. 11B and FIG. 11C, in read operation, read data D4-1 is output from memory 4 to the point m4 on data bus 9 in accordance with the clock edge t2 of clock signal Ck4, and read data D4-2 is similarly output therefrom in accordance with the clock edge t3 thereof. In addition, as shown in FIG. 11D, these read data D4-1 and D4-2 are transferred from the point m4 to the point C on data bus 9 after the passage of time tc4, and input to memory controller 5.
Meanwhile, as shown FIG. 11A and FIG. 11D, write data DC1 and DC2 are output from memory controller 5 to the point C on data bus 9 in response to the clock edges t4 and t5 of clock signal Ck0, respectively,
In this case, as shown in FIG. 11D read data D4-2 and write data DC1 conflict with each other near the point C on data bus 9. Since the data are destroyed by the conflict, a proper period (time of effective value) of read data D4-2 and write data DC1 is reduced, causing system malfunction.
In order to avoid such data conflict, waiting time of one or more clock cycles is provided between data read and write operations in data transfer in different directions. This, however, reduces the efficiency of data transfer.